In semiconductor devices, such as integrated circuits, memory is used for storing data, program code, or other information. Ferroelectric memory devices are integrated circuits (ICs), such as dedicated memories or other ICs, in which data is stored in ferroelectric cell capacitors, where the memory cells are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations. In a typical folded bitline 1T1C architecture, the individual ferroelectric memory cells include a ferroelectric (FE) capacitor adapted to store a binary data bit, together with a MOS access transistor, which operates to selectively connect the FE capacitor to one of a pair of complementary bitlines associated with an array column, with the other bitline being connected to a reference voltage for memory read operations. The memory cells are commonly organized as individual bits of a corresponding data word, where the cells of a given word are accessed concurrently along a selected array row through activation of corresponding platelines and wordlines by address decoding control circuitry.
Ferroelectric memory devices provide non-volatile data storage, wherein the memory cell capacitors are constructed using ferroelectric dielectric material that may be polarized in one direction or another in order to store a binary value. The ferroelectric effect in such cell capacitors allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the ferroelectric material. This alignment may be selectively achieved by controlled application of an electric field between the ferroelectric capacitor terminals that exceeds a coercive field of the material. Reversal of the applied field reverses the internal dipoles, wherein the response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a 1T1C ferroelectric memory cell is read by connecting a reference voltage to a first bitline (a reference bitline), and by connecting the cell capacitor between a complementary bitline (data bitline) and a plateline signal. A plateline pulse signal is then applied, whereby a differential voltage is provided on the bitline pair, which is connected to a differential sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a ferroelectric capacitor storing a binary “0” and that of the capacitor storing a binary “1”. The sensed differential voltage is buffered by the sense amp and provided to a pair of local IO lines, where the polarity of the differential voltage represents the data that was stored in the cell. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry including address decoders and timing circuits in the device.
Connection of the ferroelectric cell capacitor between the plateline pulse and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch or reverse the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, the sense amplifier can measure the charge applied to the cell bitlines and produce either a logic “1” or “0” differential voltage at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the target memory cell following each read operation. To write data to the cell in a restore or data write operation, an electric field is applied to the cell capacitor by a sense amp or write buffer to polarize it to the desired state. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption, and allow a relatively high number of write operations compared with flash and EEPROM memories.
Ferroelectric memory devices typically include a number of individually addressable memory cells arranged in an array configuration, wherein the array is typically organized as a matrix of rows and columns. Conventionally, data is stored into a memory array as a row, and read out from the memory array as a row, where the row typically consists of 8, 16, 32, or 64 bits of binary data. During a read, write, or restore memory access operation, control circuitry provides a plateline pulse signal to the first sides of the ferroelectric cells in a target array row, the other sides of which are connected to the array bitlines to provide or receive the data. In a read operation, the decoder provides plateline pulses to the first side of each ferroelectric memory cell in a target array row, and sense amplifiers are connected to the other side of the cells to sense a row of stored data bits in parallel fashion. A signal level V1 or V0 is thus obtained on the data bitline (e.g., the bitline coupled with the accessed cell), depending upon the state of the data being read (e.g., binary “1” or “0”, respectively), where the reference voltage on the other bitline is a voltage in between V1 and V0. The sense amp for each array column then amplifies (latches) the differential voltage on the complementary bitline pair. Thus, in a single memory access operation, an entire row of data bits (e.g., 8, 16, 32, or 64 bits) are obtained from the memory cells in the selected row, and the data is then provided from the sense amps to local IO circuitry. In write and restore operations, the sense amps provide the data on the bitlines and a plateline pulse is applied to the cell capacitors, whereby the data is written to the cell capacitors of the selected array row.
Thusfar, two types of reference generation schemes have been employed to provide the bitline reference voltage for read operations in ferroelectric memory devices. In the first type, a single reference generator is common to (e.g., shared by) several columns, which may be all the columns of a certain segment or other portion of the array, or a single reference generator may be shared among all the columns. A problem with this approach is that several reference bitlines are shorted together through the common reference generator during read operations. In this situation, a bad column cannot be distinguished or isolated from other (e.g., presumably good) columns, thus making replacement or substitution impossible for a single bad column where column redundancy is employed. Furthermore, a single bad column may corrupt the value of the reference voltage allied to all the columns, thereby rendering the entire array or a portion thereof unusable.
In a second approach, a separate (e.g., dedicated) reference generator is provided for each column. However, several challenges are presented in implementing the second approach, including reliability, area utilization, and power consumption. In particular, separate reference generators occupy a large amount of device area and consume a larger amount of power than do shared reference generators. Accordingly, there remains a need for improved reference generator systems and methods for providing reference voltages for ferroelectric memory devices, by which the above and other shortcomings of the prior art may be mitigated or overcome.